1. Technical Field
The disclosed embodiments relate to Digital Phase-Locked Loops (DPLLs).
2. Background Information
FIG. 1 (Prior Art) is a block diagram of a type of local oscillator 1 that sees use in generating a Local Oscillator (LO) signal within a radio transmitter. The LO may, for example, be supplied to a mixer in a transmit chain of the transmitter such that a baseband signal is upconverted in frequency for later transmission. Local oscillator 1 includes a Digital Phase-Locked Loop (DPLL) 2 followed by a programmable divider 3. DPLL 2 implements two-point modulation so that the PLL output can be modulated faster than the PLL loop bandwidth. An incoming modulating signal M(t) is provided to both a low pass modulation path and to a high pass modulation path. M(t) may, for example, be a stream of twelve-bit digital values. In the low pass modulation path, a digital summer 4 receives the modulating signal M(t) along with a relatively static channel frequency command word (FCW). The FCW may, for example, be a twenty-bit digital value. The FCW sets the center frequency of the channel to be used for transmission, whereas M(t) represents the information to be communicated. The sum of M(t) and the FCW is supplied to a reference phase accumulator 5. The value by which accumulator 5 increments on each rising edge of a clock signal of frequency fclk is the multi-bit value output by summer 4. The accumulation performed by reference phase accumulator 5 essentially converts frequency to phase. In the high pass modulation path, a scaling unit 6 receives and scales the modulating signal M(t) with a scaling factor K and provides a second modulating signal F(t). A Digitally Controlled Oscillator (DCO) 7 receives a stream of digital tuning control words S(t). DCO 7 outputs a signal DCO_OUT whose frequency is determined by the digital tuning word. For each different digital tuning word value DCO 7 might be receiving, the DCO_OUT signal has a different one of sixteen different discrete frequencies. DCO 7 may, for example, receive a reference clock signal of frequency fdco such that the DCO changes the frequency of DCO_OUT synchronously with respect to fdco. The frequencies that DCO_OUT may be controlled to have may, for example, vary within a band around four gigahertz. A Time-to-Digital Converter (TDC) 8 receives the DCO_OUT signal and a reference clock signal REF, and outputs a multi-bit digital signal X(t) whose value is proportional to the phase difference between the two signals. TDC 8 outputs one such X(t) value each period of the ftdc signal. A second summer 9 subtracts the feedback phase signal value X(t) from the modulating phase signal value P(t), thereby generating a phase error signal value E(t). A loop filter 10 filters the phase error signal. A third summer 11 sums the filtered phase error signal and the second modulating signal F(t). The output of third summer 11 is the stream of digital tuning words S(t) supplied to DCO 7. Programmable divider 3 divides the DCO_OUT signal by either two or four, depending on the band of operation, to output the Local Oscillator signal LO.
Although the DPLL of FIG. 1 may work well in a cellular telephone transmitter application, the frequency of the signal DCO_OUT changes at discrete times. These discrete times are generally equally spaced in time. This introduces what are known as “digital images”. These digital images are spectral components of the local oscillator output signal LO that are not at the desired LO main frequency. As the frequency fdco increases, the digital images move farther away in frequency from the LO main frequency, and the digital images decrease in power. Increasing the frequency fdco therefore reduces the digital image noise problem. For most cellular telephone protocols, there is a specification that sets the maximum noise allowed outside the channel in which the cellular telephone is to be transmitting. The frequency fdco is therefore kept high enough to satisfy the specification for the amount of phase noise allowed. In addition to introducing digital images into the LO signal, DPLL 2 can introduce quantization noise into the LO signal. As DPLL 2 operates, TDC 8 quantizes the phase difference between edges of the DCO_OUT signal and corresponding edges of the REF signal, and this quantization gives rise to quantization noise. If there is too much quantization noise, then the spectral purity of the LO signal is compromised to an unacceptable degree. Accordingly, TDC 8 is generally clocked at a high rate ftdc. Rate ftdc may, for example, be of the same rate fdco at which DCO 7 is clocked. Unfortunately, running DPLL 2 at these high rates can cause the DPLL to consume an undesirably large amount of power.